Currently, crystalline silicon (both multi-crystalline and mono-crystalline silicon) has the largest market share in the photovoltaics (PV) industry, currently accounting for about 85% of the overall global PV market share. Although moving to thinner crystalline silicon solar cells is long understood to be one of the most potent and effective methods for PV cost reduction (because of the relatively high material cost of crystalline silicon wafers used in solar cells as a fraction of the total PV module cost), utilizing thinner crystalline wafers is hampered by the problem of thin wafers being extremely fragile, mechanical breakage during wafer handling and cell processing, and the resulting production yield losses caused by thin and fragile silicon wafers. Other problems include inadequate light trapping in the thin cell structure because silicon is an indirect bandgap semiconductor material and absorption of longer wavelength red and infrared photons (particularly those in the wavelength range of about 900 nm to 1150 nm) requires relatively long optical path lengths—often much larger than the wafer thickness itself. Further, using known designs and manufacturing technologies it is often difficult to balance the requirement of high mechanical yield and reduced wafer breakage rate with high manufacturing yields in PV factories in a cost effective manner.
Relating to substrate (semiconductor absorber) thickness, for current crystalline silicon wafer solar cells, moving even slightly thinner than the current thickness range of 140 μm to 200 μm starts to severely compromise mechanical yield during cell and module manufacturing. This is particularly a big challenge for larger cell sizes such as 156 mm×156 mm and 210 mm×210 mm cells (compared to the smaller 125 mm×125 mm cells). Thus, manufacturable solutions directed to process very thin solar cell structures, such as with cell semiconductor absorbers thinner than about 100 μm down to micron-size-scale and submicron thickness, often must utilize a cell process during which the cell is fully supported by a either a temporary and/or a permanent host carrier throughout the process flow, or a cell process which utilizes a novel self-supporting, stand-alone, substrate with an accompanying structural innovation. This structural innovation must allow the cell substrate to be extremely robust against breakage in high throughput solar cell and module factories. Examples of the latter are the novel 3-Dimensional honeycomb and pyramidal structures formed with crystalline silicon thin films.
On the cell architecture side, back-junction/back contacted monocrystalline semiconductor (such as monocrystalline silicon) solar cells are conducive to very high efficiency. This is primarily because there is no metal shading associated losses on the front side as well as no emitter on the front which helps result in a high blue response. Moreover, the use of n-type base enables much higher mirrority carrier lifetime compared to p-type base, as well as no Light-Induced Degradation (LID). In addition, the back-contact/back-junction cell with n-type base may use well-established silicon nitride frontside passivation and anti-reflection coating layer with positive fixed charges in the passivation layer (or layer stack) comprising silicon nitride providing for improved frontside surface passivation with reduced Frontside Surface Recombination Velocity (FSRV) enabled by field-assisted passivation. Further, backside metal may be made thicker and with a higher area coverage (e.g., well over 90%) to ensure very low series resistance (or very high metal interconnect electrical conductivity) without worrying about the trade-off with shading that is often a consideration for front contacted cells. Back contacted/back junctions cells are, in particular, highly conducive to being combined with very thin (e.g., solar cell substrates for at least two distinct reasons. Firstly, high-efficiency back contacted/back junction cells have a stringent requirement of having mirrority carrier diffusion length (known as Leff) at least 5× (by a factor of at least approximately 5) the thickness of the substrate (or the active crystalline semiconductor absorber). A very thin (e.g., with crystalline semiconductor layer thickness less than about 80 microns and more preferably less than about 50 microns) solar cell substrate enables this requirement without demanding a very high bulk substrate lifetime or a very high quality material, thus, can be done in practice on a cheaper starting material having eliminated the most stringent substrate quality requirements. This indirectly gives a further cost advantage: the quality of the material can be relaxed in addition to it being thinner. A second reason is related to the process flow which enables fabrication of the back contact/back junction cells (will be discussed further in the following sections). Because back contacted cell architecture and related process flow may be catered to have all high temperature process steps (i.e., any cell process steps with process temperatures in the range of approximately 400° C. to ˜1150° C.) on one side of the cell, the requirement for a carrier of the thin substrate when it is going through processing on the other sides are considerably eased. Thus, using a very thin substrate (e.g., with crystalline semiconductor layer thickness less than about 80 microns and more preferably less than about 50 microns) in conjunction with a back-contacted/back-junction architecture may represent an ideal solar cell combination.
In the past, there have been attempts in solar PV R&D to use carriers such as glass for thin substrates; however, these carriers have suffered from serious limitations including relatively low maximum processing temperatures in the case of soda lime glass (or most other non-silicon foreign materials), with the processing temperatures being limited to well below approximately 400° C.—which potentially may compromise the solar cell efficiency. There have also been attempts to make small area (for example, cell areas well below 10 cm2) thin cells which do not have serious breakage concerns (while they still suffer from the thermal processing limitations, including limitation of process temperatures to well below approximately 400° C.); however, large cell areas (areas well above 100 cm2) are often required for commercial viability through cost-effective manufacturing.